134 lines
2.9 KiB
ArmAsm
134 lines
2.9 KiB
ArmAsm
; Copyright 2021 KoroLion (https://github.com/KoroLion)
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#define __SFR_OFFSET 0
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#define LED_PORT 7
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#include "avr/io.h" // ~ #include "avr/iom328p.h"
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.section .bss
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lm35_port: .byte 0
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.section .text
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.global lm35_init
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.global lm35_read
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.global led_init
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.global led_enable
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.global led_disable
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led_init:
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sbi DDRD, LED_PORT
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ret
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led_enable:
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sbi PORTD, LED_PORT
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ret
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led_disable:
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cbi PORTD, LED_PORT
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ret
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.macro pin_mode_input port
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; sets analog port as input
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ldi r31, 1 ; means port 0
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cpi \port, 0
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breq end_convert ; = 0 => no need to convert (already set mask to port 0)
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mov r30, \port
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convert:
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lsl r31 ; logic shift left ~ r31 * 2
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dec r30
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cpi r30, 0
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brne convert
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end_convert:
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com r31 ; inverting mask (00001000 -> 11110111)
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; setting correct DDRC using mask
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in r30, DDRC
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and r30, r31 ; applying mask (11111111 and 11110111 = 11110111)
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out DDRC, r30
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.endm
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.macro adc_read port, res_high, res_low
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ldi r30, 0b00000000
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sts PRR, r30
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; first two bits are for the ref voltage
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; 11 means using internal 1.1v atmega voltage for adc
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; last three bits are for the analog port number
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ldi r30, 0b11000000
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or r30, \port
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sts ADMUX, r30
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; last 3 bits (111 means 128)
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; ADC Prescaler Select Bits (ADPS): ADPS2, ADPS1 and ADPS0 bits are used to set circuit clock frequency.
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; For ADC circuitry to work at its maximum resolution needs to be supplied with 50 kHz to 200 kHz frequency as per the datasheet;
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; but the system clock will be generally higher (8 MHz, 10 MHz, 16 MHz etc).
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; To reduce it to required frequency we use ADC prescaler bits. Suppose we have system clock with frequency 10Mhz (10000000 Hz) and set division factor to 64,
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; then ADC clock frequency is 10000000/64 = 156250Hz = 156.25 KHz, which is between 50 to 200 KHz as mentioned in the datasheet.
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; (http://www.robotplatform.com/knowledge/ADC/adc_tutorial_2.html)
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;
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; 16 MHz / 128 = 16000000 Hz / 128 = 125000 Hz = 125 KHz => OK!
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ldi r30, 0b11000111
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sts ADCSRA, r30
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wait_adc:
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lds r30, ADCSRA
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ldi r31, 0b01000000
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and r31, r30
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cpi r31, 0
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brne wait_adc
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lds \res_low, ADCL
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lds \res_high, ADCH
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; clearing unused bits to be sure they're zero
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ldi r31, 0b00000011
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and \res_high, r31
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.endm
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.macro divw10 divident_high, divident_low
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; r30 - res
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; divident_low - quotient
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ldi r30, 0
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division:
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cpi \divident_low, 10
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brlo division_low_end ; <
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continue_division:
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sbiw \divident_low, 10
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inc r30
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rjmp division
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division_low_end:
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cpi \divident_high, 0
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brne continue_division
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cpi \divident_low, 5
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brlo not_inc ; <
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inc r30
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not_inc:
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.endm
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lm35_init:
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; r25:r24 is the first arg
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subi r24, 14 ; because A0 is D14
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pin_mode_input r24
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sts lm35_port, r24
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ret
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lm35_read:
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cli ; forbids interruptions
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lds r24, lm35_port
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adc_read r24, r25, r24
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divw10 r25, r24
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mov r24, r30 ; uint8_t return value
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adiw r24, 2 ; due to LM35 formula (2C to 150C)
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sei ; allow interruptions
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clr r1 ; c requirement
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ret
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